Design Trends and Perspectives of Digital Low Dropout Voltage Regulators for Low Voltage Mobile Applications: A Review

Low-dropout (LDO) voltage regulator has fascinated industry professionals and academia for the past few decades, this trend is expected to continue in coming years. The high demand a stable linear architecture that performs well systems-on-chip (SoC) power management integrated circuits (PMICs) key factor driving innovation with different complementary metal-oxide-semiconductor (CMOS) technologies. Yet, there are several performance parameter trade-offs be considered, such as transient response, output ripple, area, efficiency, supply range, current efficiency LDO design architecture. All these become more severe during back-end CMOS processes additional limitations, example, channel length modulation, stress sensitivity, leakage, among others. Therefore, paper presents an overview comparison of various digital (DLDO) topologies, functionalities, specifications, which can serve virtual study or reference